Beta Processor

 

 

Project Description

For this project we’re asking you to optimize the price/performance of your Beta design. The “price” is determined from the area of your circuit as reported by JSim at the end of each simulation run (it reports the size in square microns in the message area at the bottom of the netlist window). The “performance” is determined by the time needed to complete a set of benchmark programs. Benchmarking is the traditional, if somewhat unreliable, way of characterizing processor performance. The benchmark suite can be found using the online BSim at /shared/bsim/projcheckoff.uasm; in addition to a short functional test, it includes four benchmarks:

 

• Benchmark #1 makes two calls to a subroutine that performs an unsigned divide of its arguments, and then stores the quotients and remainders in main memory.

• Benchmark #2 makes two subroutine calls: one to do an in-place reverse an 11-element list, the second to compare the reversed list with an "answer" list to see if all went well.

• Benchmark #3 makes a copy of itself further up in memory and then jumps to the first location of the copy. The process is repeated 2 times.

• Benchmark #4 just performs a lot register arithmetic and writes the result to memory -- should be a slam dunk for pipelined and superscalar machines.

 

See projcheckoff.uasm for details about what values are written by each benchmark. The suite requires 1104 cycles to execute on a standard unpipelined Beta. Start by giving it plenty of time to run the benchmark; you’ll recognize its completion by the 1-instruction BEQ loop at 0x44. You can then trim run time down to just get to this BEQ, to maximize your score. Note: Long simulations of big circuits can produce very large history files, so it can take a while to prepare the waveform plots at the end of your simulation. Be patient and be modest in the number of signals you choose to plot. 6.004 Computation Structures - 2 - Design Project Since your optimized design may operate differently than the Beta described in the Lab handouts, the checkoff file (/mit/6.004/jsim/projcheckoff.jsim) is a little different than the others we’ve seen so far this semester. It contains no test circuitry at all; you’ll need to provide the main memory, waveform generators for CLK and RESET, etc. – whatever your optimized design needs to execute correctly. The only constraint on your netlist is that you must provide a 32-bit wide, 1024 location main memory called Xmem to store the benchmark program and hold the results. The checkoff file checks certain locations of this memory to see that the benchmark has completed successfully. If your design passes verification, you can submit it to the on-line checkoff system which will report the number of points your design has received. The points are determined by the following formula:

 

Benmark® = 1e-10/(<ending simulation time in seconds>*<size of circuit in meter2>)

 

Points = round(Benmark − 13) [rounded; min = 0, max = 25]

 

The smaller your circuit and the faster it completes the benchmark, the better the Benmark. A good Beta design completed as described in the Lab handouts has a Benmark of 15 or more (depending on various design choices) and would receive several points if submitted. So you’ll need to do some modest innovation to max out on points – see the Hints section for some suggestions.